17.16 UDDRC CRC Parity Status Register
Name: | UDDRC_CRCPARSTAT |
Offset: | 0x0CC |
Reset: | 0x00000000 |
Property: | Read-only |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
DFI_ALERT_ERR_INT | |||||||||
Access | R | ||||||||
Reset | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
DFI_ALERT_ERR_CNT[15:8] | |||||||||
Access | R | R | R | R | R | R | R | R | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
DFI_ALERT_ERR_CNT[7:0] | |||||||||
Access | R | R | R | R | R | R | R | R | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 16 – DFI_ALERT_ERR_INT DFI Alert Error Interrupt
If a parity/CRC error is detected on dfi_alert_n, and the interrupt is enabled by CRCPARCTL0.dfi_alert_err_int_en, this interrupt bit will be set. It will remain set until cleared by CRCPARCTL0.dfi_alert_err_int_clr.
Programming Mode: Static
Bits 15:0 – DFI_ALERT_ERR_CNT[15:0] DFI Alert Error Count
If a parity/CRC error is detected on dfi_alert_n, this counter be incremented. This is independent of the setting of CRCPARCTL0.dfi_alert_err_int_en. It will saturate at 0xFFFF, and can be cleared by asserting CRCPARCTL0.dfi_alert_err_cnt_clr.
Programming Mode: Static