17.42 UDDRC DFI Update Register 0
| Name: | UDDRC_DFIUPD0 |
| Offset: | 0x1A0 |
| Reset: | 0x00400003 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| DIS_AUTO_CTRLUPD | DIS_AUTO_CTRLUPD_SRX | CTRLUPD_PRE_SRX | DFI_T_CTRLUP_MAX[9:8] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DFI_T_CTRLUP_MAX[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DFI_T_CTRLUP_MIN[9:8] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DFI_T_CTRLUP_MIN[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | |
Bit 31 – DIS_AUTO_CTRLUPD
When '1', disable the automatic dfi_ctrlupd_req generation by the UDDRC. The core must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd.
When '0', UDDRC issues dfi_ctrlupd_req periodically.
Programming Mode: Quasi-dynamic Group 3
Bit 30 – DIS_AUTO_CTRLUPD_SRX
When '1', disable the automatic dfi_ctrlupd_req generation by the UDDRC at self-refresh exit.
When '0', UDDRC issues a dfi_ctrlupd_req before or after exiting self-refresh, depending on DFIUPD0.ctrlupd_pre_srx.
Programming Mode: Static
Bit 29 – CTRLUPD_PRE_SRX
Selects dfi_ctrlupd_req requirements at SRX:
If DFIUPD0.dis_auto_ctrlupd_srx=1, this register has no impact, because no dfi_ctrlupd_req will be issued when SRX.
Programming Mode: Static
| Value | Description |
|---|---|
| 0 | Send ctrlupd after SRX. |
| 1 | Send ctrlupd before SRX. |
Bits 25:16 – DFI_T_CTRLUP_MAX[9:0]
Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40.
Unit: DFI clock cycles.
Programming Mode: Static
Bits 9:0 – DFI_T_CTRLUP_MIN[9:0]
Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The UDDRC expects the PHY to respond within this time. If the PHY does not respond, the UDDRC will de-assert dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3.
Unit: DFI clock cycles.
Programming Mode: Static