17.5 UDDRC Mode Register Read/Write Status Register

Name: UDDRC_MRSTAT
Offset: 0x018
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
        MR_WR_BUSY 
Access R 
Reset 0 

Bit 0 – MR_WR_BUSY

The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the UDDRC accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when 'MRSTAT.mr_wr_busy' is high.

Programming mode: Dynamic

ValueDescription
0 Indicates that the SoC core can initiate a mode register write operation.
1 Indicates that mode register write operation is in progress.