17.5 UDDRC Mode Register Read/Write Status Register
Name: | UDDRC_MRSTAT |
Offset: | 0x018 |
Reset: | 0x00000000 |
Property: | Read-only |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
Access | |||||||||
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
MR_WR_BUSY | |||||||||
Access | R | ||||||||
Reset | 0 |
Bit 0 – MR_WR_BUSY
Programming mode: Dynamic
Value | Description |
---|---|
0 | Indicates that the SoC core can initiate a mode register write operation. |
1 | Indicates that mode register write operation is in progress. |