17.60 UDDRC Scheduler Control Register 1
| Name: | UDDRC_SCHED1 |
| Offset: | 0x254 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PAGECLOSE_TIMER[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:0 – PAGECLOSE_TIMER[7:0]
This field works in conjunction with UDDRC_SCHED.PAGECLOSE.
It only has meaning if UDDRC_SCHED.PAGECLOSE=1.
If UDDRC_SCHED.PAGECLOSE=1 and UDDRC_SCHED1.PAGECLOSE=0, then an auto-precharge may be scheduled for last read or write command in the CAM with a bank and page hit.
Note, sometimes an explicit precharge is scheduled instead of the auto-precharge. See UDDRC_SCHED.PAGECLOSE for details of when this may happen.
If UDDRC_SCHED.PAGECLOSE=1 and PAGECLOSE_TIMER>0, then an auto-precharge is not scheduled for last read or write command in the CAM with a bank and page hit.
Instead, a timer is started, with PAGECLOSE_TIMER as the initial value.
There is a timer on a per bank basis.
The timer decrements unless the next read or write in the CAM to a bank is a page hit.
It gets reset to PAGECLOSE_TIMER value if the next read or write in the CAM to a bank is a page hit.
Once the timer has reached zero, an explicit precharge will be attempted to be scheduled.
Unit: DFI clock cycles.
Programming Mode: Static