17.15 UDDRC CRC Parity Control Register 0

Note: Do not perform any APB access to CRCPARCTL0 within 32 pclk cycles of previous access to CRCPARCTL0, as this might lead to data loss.
Name: UDDRC_CRCPARCTL0
Offset: 0x0C0
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
      DFI_ALERT_ERR_CNT_CLRDFI_ALERT_ERR_INT_CLRDFI_ALERT_ERR_INT_EN 
Access R/WR/WR/W 
Reset 000 

Bit 2 – DFI_ALERT_ERR_CNT_CLR DFI Alert Error Count Clear

Clear bit for DFI alert error counter. Asserting this bit will clear the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. UDDRC automatically clears this bit.

Programming mode: Dynamic

Bit 1 – DFI_ALERT_ERR_INT_CLR Interrupt Clear Bit for DFI Alert Error

If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int will be cleared. UDDRC automatically clears this bit.

Programming mode: Dynamic

Bit 0 – DFI_ALERT_ERR_INT_EN Interrupt enable bit for DFI alert error

If this bit is set, any parity/CRC error detected on the dfi_alert_n input will result in an interrupt being set on CRCPARSTAT.dfi_alert_err_int.

Programming mode: Dynamic