17.30 UDDRC SDRAM Timing Register 6

Name:	UDDRC_DRAMTMG6
Offset:	0x118
Reset:	0x02020005
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
					T_CKDPDE[3:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	1	0


Bit	23	22	21	20	19	18	17	16
					T_CKDPDX[3:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	1	0


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
					T_CKCSX[3:0]
Access					R/W	R/W	R/W	R/W
Reset					0	1	0	1

Bits 27:24 – T_CKDPDE[3:0]

This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE.

Recommended settings:

- LPDDR2: 2

- LPDDR3: 2

When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer.

This is only present for designs supporting LPDDR2/LPDDR3 devices.

Unit: DFI clock cycles.

Programming Mode: Quasi-dynamic Group 2, Group 4

Bits 19:16 – T_CKDPDX[3:0]

This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX.

Recommended settings:

- LPDDR2: 2

- LPDDR3: 2

When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer.

This is only present for designs supporting LPDDR2 devices.

Unit: DFI clock cycles.

Programming Mode: Quasi-dynamic Group 2, Group 4

Bits 3:0 – T_CKCSX[3:0]

This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit.

Recommended settings:

- LPDDR2: tXP + 2

- LPDDR3: tXP + 2

When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer.

This is only present for designs supporting LPDDR2/LPDDR3 devices.

Unit: DFI clock cycles.

Programming Mode: Quasi-dynamic Group 2, Group 4