17.40 UDDRC DFI Timing Register 1

Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven.

Unit: DFI PHY clock cycles.

Programming Mode: Quasi-dynamic Group 4

Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus.

This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification for correct value.

For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0.

For DFI 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM).

Value to be programmed is in terms of DFI clocks, not PHY clocks.

In FREQ_RATIO=2, divide PHY's value by 2 and round up to next integer.

If using DFITMG0.dfi_wrdata_use_dfi_phy_clk=1, add 1 to the value.

Unit: DFI clock cycles.

Programming Mode: Quasi-dynamic Group 4

Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value.

Unit: DFI clock cycles.

Programming Mode: Quasi-dynamic Group 4

Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value.

Unit: DFI clock cycles.

Programming Mode: Quasi-dynamic Group 4