17.17 UDDRC SDRAM Initialization Register 0
| Name: | UDDRC_INIT0 |
| Offset: | 0x0D0 |
| Reset: | 0x0002004E |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SKIP_DRAM_INIT[1:0] | POST_CKE_X1024[9:8] | ||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| POST_CKE_X1024[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PRE_CKE_X1024[11:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PRE_CKE_X1024[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | |
Bits 31:30 – SKIP_DRAM_INIT[1:0]
Programming mode: Quasi-dynamic Group 2
| Value | Description |
|---|---|
| 00 | SDRAM Initialization routine is run after power-up. |
| 01 | SDRAM Initialization routine is skipped after power-up. Controller starts up in Normal mode. |
| 11 | SDRAM Initialization routine is skipped after power-up. Controller starts up in Self-refresh mode. |
| 10 | Reserved |
Bits 25:16 – POST_CKE_X1024[9:0]
DDR2 typically requires a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds.
LPDDR2/LPDDR3 typically requires this to be programmed for a delay of 200 µs.
When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value.
Unit: Multiples of 1024 DFI clock cycles.
Programming mode: Static
Bits 11:0 – PRE_CKE_X1024[11:0]
DDR2 specifications typically require this to be programmed for a delay of ≥200 µs.
LPDDR2/LPDDR3: tINIT1 of 100 ns (min)
When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value.
For DDR3 RDIMMs, this should include the time needed to satisfy tSTAB.
Unit: Multiples of 1024 DFI clock cycles.
Programming mode: Static