17.34 UDDRC SDRAM Timing Register 15
| Name: | UDDRC_DRAMTMG15 |
| Offset: | 0x13C |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| EN_DFI_LP_T_STAB | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| T_STAB_X32[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 31 – EN_DFI_LP_T_STAB
Programming Mode: Quasi-dynamic Group 2, Group 4
| Value | Description |
|---|---|
| 0 | Disable using tSTAB when exiting DFI LP. |
| 1 | Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power. |
Bits 7:0 – T_STAB_X32[7:0] tSTAB: Stabilization time.
It is required in the following two cases for DDR3 RDIMM:
- when exiting power saving mode, if the clock was stopped, after re-enabling it the clock must be stable for a time specified by tSTAB
- after issuing control words that refers to clock timing
(Specification: 6 µs for DDR3)
When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer.
Unit: Multiples of 32 DFI clock cycles.
Programming Mode: Quasi-dynamic Group 2, Group 4