17.29 UDDRC SDRAM Timing Register 5
| Name: | UDDRC_DRAMTMG5 |
| Offset: | 0x114 |
| Reset: | 0x05050403 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| T_CKSRX[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 1 | 0 | 1 | |||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| T_CKSRE[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 1 | 0 | 1 | |||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| T_CKESR[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 1 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| T_CKE[4:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 1 | 1 | ||||
Bits 27:24 – T_CKSRX[3:0]
This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX.
Recommended settings:
- LPDDR2: 2
- LPDDR3: 2
- DDR2: 1
- DDR3: tCKSRX
When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer.
Unit: DFI clock cycles.
Programming Mode: Quasi-dynamic Group 2, Group 4
Bits 19:16 – T_CKSRE[3:0]
This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE.
Recommended settings:
- LPDDR2: 2
- LPDDR3: 2
- DDR2: 1
- DDR3: max (10 ns, 5 tCK)
Unit: DFI clock cycles.
Programming Mode: Quasi-dynamic Group 2, Group 4
Bits 13:8 – T_CKESR[5:0]
Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles.
Recommended settings:
- LPDDR2: tCKESR
- LPDDR3: tCKESR
- DDR2: tCKE
- DDR3: tCKE + 1
Unit: DFI clock cycles.
Programming Mode: Quasi-dynamic Group 2, Group 4
Bits 4:0 – T_CKE[4:0]
Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh.
- LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR
- Non-LPDDR2/non-LPDDR3 designs: Set this to tCKE value.
When the controller is operating in 1:2 frequency ratio mode, program this to (value described above)/2 and round it up to the next integer value.
Unit: DFI clock cycles.
Programming Mode: Quasi-dynamic Group 2, Group 4