17.50 UDDRC Address Map Register 3


Bit	31	30	29	28	27	26	25	24
				ADDRMAP_COL_B9[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
				ADDRMAP_COL_B8[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
				ADDRMAP_COL_B7[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
				ADDRMAP_COL_B6[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0

Bits 28:24 – ADDRMAP_COL_B9[4:0]

- Full bus width mode: Selects the HIF address bit used as column address bit 9.

- Half bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode).

- Quarter bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode).

Valid Range: 0 to 7, and 31.

Internal Base: 9

The selected HIF address bit is determined by adding the internal base to the value of this field.

In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used.

If column bit 9 is the highest column address bit, it must map to the highest valid HIF address bit. (x = the highest valid HIF address bit - internal base)

If column bit 9 is the second highest column address bit, it must map to the second highest valid HIF address bit. (x = the highest valid HIF address bit - 1 - internal base)

If column bit 9 is the third highest column address bit, it must map to the third highest valid HIF address bit. (x = the highest valid HIF address bit - 2 - internal base)

If unused, set to 31 and then this column address bit is set to 0.

Programming Mode: Static

Note: Per JEDEC DDR2/3 specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.

Bits 20:16 – ADDRMAP_COL_B8[4:0]

- Full bus width mode: Selects the HIF address bit used as column address bit 8.

- Half bus width mode: Selects the HIF address bit used as column address bit 9.

- Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode).

Valid Range: 0 to 7, and 31.

Internal Base: 8

The selected HIF address bit is determined by adding the internal base to the value of this field.

In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used.

If column bit 8 is the second highest column address bit, it must map to the second highest valid HIF address bit. (x = the highest valid HIF address bit - 1 - internal base)

If column bit 8 is the third highest column address bit, it must map to the third highest valid HIF address bit. (x = the highest valid HIF address bit - 2 - internal base)

If unused, set to 31 and then this column address bit is set to 0.

Programming Mode: Static

Note: Per JEDEC DDR2/3 specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.

Bits 12:8 – ADDRMAP_COL_B7[4:0]

- Full bus width mode: Selects the HIF address bit used as column address bit 7.

- Half bus width mode: Selects the HIF address bit used as column address bit 8.

- Quarter bus width mode: Selects the HIF address bit used as column address bit 9.

Valid Range: 0 to 7, and 31.

Internal Base: 7

The selected HIF address bit is determined by adding the internal base to the value of this field.

If column bit 7 is the third highest column address bit, it must map to the third highest valid HIF address bit. (x = the highest valid HIF address bit - 2 - internal base)

If unused, set to 31 and then this column address bit is set to 0.

Programming Mode: Static

Bits 4:0 – ADDRMAP_COL_B6[4:0]

- Full bus width mode: Selects the HIF address bit used as column address bit 6.

- Half bus width mode: Selects the HIF address bit used as column address bit 7.

- Quarter bus width mode: Selects the HIF address bit used as column address bit 8.

Valid Range: 0 to 7.

Internal Base: 6

The selected HIF address bit is determined by adding the internal base to the value of this field.

If unused, set to 31 and then this column address bit is set to 0.

Programming Mode: Static

Name:	UDDRC_ADDRMAP3
Offset:	0x20C
Reset:	0x00000000
Property:	Read/Write