17.11 UDDRC Hardware Low Power Control Register

Name:	UDDRC_HWLPCTL
Offset:	0x038
Reset:	0x00000003
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
					HW_LP_IDLE_X32[11:8]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	23	22	21	20	19	18	17	16
	HW_LP_IDLE_X32[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
							HW_LP_EXIT_IDLE_EN	HW_LP_EN
Access							R/W	R/W
Reset							1	1

Bits 27:16 – HW_LP_IDLE_X32[11:0] Hardware Idle Period

The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in Init or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware idle function is disabled when hw_lp_idle_x32=0. hw_lp_idle_x32=1 is an illegal value.

For performance only.

Unit: Multiples of 32 DFI clock cycles.

Programming mode: Static

Bit 1 – HW_LP_EXIT_IDLE_EN

When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the Automatic Clock Stop, Automatic Power-down or Automatic Self-refresh modes. Note, it will not cause exit of Self-refresh that was caused by hardware low-power Interface and/or software (PWRCTL.selfref_sw).

Programming mode: Static

Bit 0 – HW_LP_EN Enable for Hardware Low Power Interface

Programming mode: Quasi-dynamic Group 2