17.6 UDDRC Temperature Derate Enable Register
| Name: | UDDRC_DERATEEN |
| Offset: | 0x020 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DERATE_MR4_TUF_DIS | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DERATE_BYTE[3:0] | DERATE_VALUE[1:0] | DERATE_ENABLE | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bit 12 – DERATE_MR4_TUF_DIS
For LPDDR2 and LPDDR3, contact your memory vendor for recommended usage.
This affects both the periodic derate logic (DERATEEN.derate_enable) and the derate_temp_limit_intr.
Programming mode: Quasi-dynamic Group 2, Group 4
| Value | Description |
|---|---|
| 0 | Use MR4 TUF flag (MR4[7]). |
| 1 | Do not use MR4 TUF Flag (MR4[7]). |
Bits 7:4 – DERATE_BYTE[3:0] Derate byte
Present only in designs configured to support LPDDR2/LPDDR3.
Indicates which byte of the MRR data is used for derating. The maximum valid value is 1.
Programming mode: Static
Bits 2:1 – DERATE_VALUE[1:0] Derate value
Present only in designs configured to support LPDDR2/LPDDR3.
Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period.
For LPDDR3, if the period of core_ddrc_core_clk is less than 1.875ns, this register field should be set to 1; otherwise it should be set to 0.
Programming mode: Quasi-dynamic Group 2, Group 4
| Value | Description |
|---|---|
| 0 | Derating uses +1 |
| 1 | Derating uses +2 |
Bit 0 – DERATE_ENABLE Enables derating
Present only in designs configured to support LPDDR2/LPDDR3.
This field must be set to '0' for non-LPDDR2/LPDDR3 mode.
Programming mode: Dynamic
| Value | Description |
|---|---|
| 0 | Timing parameter derating is disabled. |
| 1 | Timing parameter derating is enabled using MR4 read value. |