17.97 UDDRC AXI Port 3 Configuration Read Register
| Name: | UDDRC_PCFGR_3 |
| Offset: | 0x614 |
| Reset: | 0x00004000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RD_PORT_PAGEMATCH_EN | RD_PORT_URGENT_EN | RD_PORT_AGING_EN | RD_PORT_PRIORITY[9:8] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 1 | 0 | 0 | 0 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RD_PORT_PRIORITY[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 14 – RD_PORT_PAGEMATCH_EN
If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (same bank and same row). See also UDDRC_PCCFG.PAGEMATCH_LIMIT.
Programming Mode: Static
Bit 13 – RD_PORT_URGENT_EN
If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the host, that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command).
Programming Mode: Static
Bit 12 – RD_PORT_AGING_EN
If set to 1, enables aging function for the read channel of the port.
Programming Mode: Static
Bits 9:0 – RD_PORT_PRIORITY[9:0]
Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis.
Programming Mode: Static