17.22 UDDRC SDRAM Initialization Register 5
| Name: | UDDRC_INIT5 |
| Offset: | 0x0E4 |
| Reset: | 0x00100004 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DEV_ZQINIT_X32[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| MAX_AUTO_INIT_X1024[9:8] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MAX_AUTO_INIT_X1024[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | |
Bits 23:16 – DEV_ZQINIT_X32[7:0]
ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or LPDDR2/LPDDR3.
DDR3 typically requires 512 SDRAM clock cycles.
LPDDR2/LPDDR3 requires 1 µs.
When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value.
Unit: Multiples of 32 DFI clock cycles.
Programming Mode: Static
Bits 9:0 – MAX_AUTO_INIT_X1024[9:0]
Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3.
LPDDR2/LPDDR3 typically requires 10 µs.
Unit: Multiples of 1024 DFI clock cycles.
Programming Mode: Static