17.36 UDDRC ZQ Control Register 1
| Name: | UDDRC_ZQCTL1 |
| Offset: | 0x184 |
| Reset: | 0x02000100 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| T_ZQ_RESET_NOP[9:4] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 1 | 0 | |||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| T_ZQ_RESET_NOP[3:0] | T_ZQ_SHORT_INTERVAL_X1024[19:16] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| T_ZQ_SHORT_INTERVAL_X1024[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| T_ZQ_SHORT_INTERVAL_X1024[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 29:20 – T_ZQ_RESET_NOP[9:0]
tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM.
When the controller is operating in 1:2 frequency ratio mode, program this to tZQReset/2 and round it up to the next integer value.
This is only present for designs supporting LPDDR2/LPDDR3 devices.
Unit: DFI clock cycles.
Programming Mode: Static
Bits 19:0 – T_ZQ_SHORT_INTERVAL_X1024[19:0]
Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/LPDDR2/LPDDR3 devices.
Meaningless, if ZQCTL0.dis_auto_zq=1.
This is only present for designs supporting DDR3 or LPDDR2/LPDDR3 devices.
Unit: Multiples of 1024 DFI clock cycles.
Programming Mode: Static