17.10 UDDRC Low Power Timing Register


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
	SELFREF_TO_X32[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	1	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	T_DPD_X4096[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	1	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
				POWERDOWN_TO_X32[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				1	0	0	0	0

Bits 23:16 – SELFREF_TO_X32[7:0]

After this many clocks of the DDRC command channel being idle the UDDRC automatically puts the SDRAM into Self-refresh.

The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en.

For performance only.

Unit: Multiples of 32 DFI clock cycles.

Programming mode: Quasi-dynamic Group 4

Bits 15:8 – T_DPD_X4096[7:0] Minimum deep power-down time

For LPDDR2/LPDDR3, value from the JEDEC specification is 500 µs.

Present only in designs configured to support LPDDR2 or LPDDR3.

For performance only.

Unit: Multiples of 4096 DFI clock cycles.

Programming mode: Quasi-dynamic Group 4

Bits 4:0 – POWERDOWN_TO_X32[4:0]

After this many clocks of the DDRC command channel being idle the UDDRC automatically puts the SDRAM into Power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en.

For performance only.

Unit: Multiples of 32 DFI clock cycles.

Programming mode: Quasi-dynamic Group 4

Name:	UDDRC_PWRTMG
Offset:	0x034
Reset:	0x00402010
Property:	Read/Write