17.68 UDDRC Status Debug Register

Name: UDDRC_DBGSTAT
Offset: 0x310
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
   CTRLUPD_BUSYZQ_CALIB_SHORT_BUSY   RANK0_REFRESH_BUSY 
Access RRR 
Reset 000 

Bit 5 – CTRLUPD_BUSY

SoC core may initiate a ctrlupd operation only if this signal is low.

This signal goes high in the clock after the UDDRC accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the UDDRC.

It is recommended not to perform ctrlupd operations when this signal is high.

Programming Mode: Dynamic

ValueDescription
0 Indicates that the SoC core can initiate a ctrlupd operation.
1 Indicates that ctrlupd operation has not been initiated yet in the UDDRC.

Bit 4 – ZQ_CALIB_SHORT_BUSY

SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the UDDRC accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the UDDRC. It is recommended not to perform ZQCS operations when this signal is high.

Programming Mode: Dynamic

ValueDescription
0 Indicates that the SoC core can initiate a ZQCS operation.
1 Indicates that ZQCS operation has not been initiated yet in the UDDRC.

Bit 0 – RANK0_REFRESH_BUSY

SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low.

This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in the UDDRC.

It is recommended not to perform rank0_refresh operations when this signal is high.

Programming Mode: Dynamic

ValueDescription
0 Indicates that the SoC core can initiate a rank0_refresh operation.
1 Indicates that rank0_refresh operation has not been stored yet in the UDDRC.