17.43 UDDRC DFI Update Register 1
| Name: | UDDRC_DFIUPD1 |
| Offset: | 0x1A4 |
| Reset: | 0x00010001 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DFI_T_CTRLUPD_INTERVAL_MIN_X1024[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DFI_T_CTRLUPD_INTERVAL_MAX_X1024[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | |
Bits 23:16 – DFI_T_CTRLUPD_INTERVAL_MIN_X1024[7:0]
This is the minimum amount of time between UDDRC initiated DFI update requests (which is executed whenever the UDDRC is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the UDDRC is idle. Minimum allowed value for this field is 1.
Unit: Multiples of 1024 DFI clock cycles.
Programming Mode: Static
Bits 7:0 – DFI_T_CTRLUPD_INTERVAL_MAX_X1024[7:0]
This is the maximum amount of time between UDDRC initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Minimum allowed value for this field is 1.
Unit: Multiples of 1024 DFI clock cycles.
Programming Mode: Static