17.28 UDDRC SDRAM Timing Register 4

Name:	UDDRC_DRAMTMG4
Offset:	0x110
Reset:	0x05040405
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
				T_RCD[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	1	0	1


Bit	23	22	21	20	19	18	17	16
					T_CCD[3:0]
Access					R/W	R/W	R/W	R/W
Reset					0	1	0	0


Bit	15	14	13	12	11	10	9	8
					T_RRD[3:0]
Access					R/W	R/W	R/W	R/W
Reset					0	1	0	0


Bit	7	6	5	4	3	2	1	0
				T_RP[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	1	0	1

Bits 28:24 – T_RCD[4:0] tRCD - tAL: Minimum time from activate to read or write command to same bank.

When the controller is operating in 1:2 frequency ratio mode, program this to ((tRCD - tAL)/2) and round it up to the next integer value.

Minimum value allowed for this register is 1, which implies minimum (tRCD - tAL) value to be 2 when the controller is operating in 1:2 frequency ratio mode.

Unit: DFI clock cycles.

Programming Mode: Quasi-dynamic Group 1, Group 2, Group 4

Bits 19:16 – T_CCD[3:0] tCCD: This is the minimum time between two reads or two writes

When the controller is operating in 1:2 frequency ratio mode, program this to (tCCD_L/2 or tCCD/2) and round it up to the next integer value.

Unit: DFI clock cycles.

Programming Mode: Quasi-dynamic Group 2, Group 4

Bits 11:8 – T_RRD[3:0] tRRD: Minimum time between activates from bank "a" to bank "b"

When the controller is operating in 1:2 frequency ratio mode, program this to (tRRD_L/2 or tRRD/2) and round it up to the next integer value.

Unit: DFI clock cycles.

Programming Mode: Quasi-dynamic Group 2, Group 4

Bits 4:0 – T_RP[4:0] tRP: Minimum time from single-bank precharge to activate of same bank.

When the controller is operating in 1:1 frequency ratio mode, t_rp should be set to RoundUp(tRP/tCK).

When the controller is operating in 1:2 frequency ratio mode, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + 1.

Unit: DFI clock cycles.

Programming Mode: Quasi-dynamic Group 2, Group 4