21.5.58 MSS DDR Bridge Disable Buffer Status Register

Table 21-66. DDRB_DSBL_DN_SR
Bit Number Name Reset Value Description
[31:7] Reserved 0
6 DDRB_IDC_DSBL_DN 0 Is set to ‘1’ once the AHB bus matrix read buffer is disabled after getting a read buffer disable command from processor.
5 DDRB_HPD_RDSBL_DN 0 Is set to ‘1’ once the HPDMA read buffer is disabled after getting a read buffer disable command from processor.
4 DDRB_HPD_WDSBL_DN 0 Is set to ‘1’ once the HPDMA write buffer is disabled after getting a write buffer disable command from processor.
3 DDRB_SW_RDSBL_DN 0 Is set to ‘1’ once the AHB bus matrix read buffer is disabled after getting a read buffer disable command from processor.
2 DDRB_SW_WDSBL_DN 0 Is set to ‘1’ once the AHB bus matrix write buffer is disabled after getting a write buffer disable command from processor.
1 DDRB_DS_RDSBL_DN 0 Is set to ‘1’ once the DS read buffer is disabled after getting a read buffer disable command from processor.
0 DDRB_DS_WDSBL_DN 0 Is set to ‘1’ once the DS write buffer is disabled after getting a write buffer disable command from processor.