21.5.58 MSS DDR Bridge Disable Buffer Status Register

Table 21-66. DDRB_DSBL_DN_SR
Bit NumberNameReset ValueDescription
[31:7]Reserved0
6DDRB_IDC_DSBL_DN0Is set to ‘1’ once the AHB bus matrix read buffer is disabled after getting a read buffer disable command from processor.
5DDRB_HPD_RDSBL_DN0Is set to ‘1’ once the HPDMA read buffer is disabled after getting a read buffer disable command from processor.
4DDRB_HPD_WDSBL_DN0Is set to ‘1’ once the HPDMA write buffer is disabled after getting a write buffer disable command from processor.
3DDRB_SW_RDSBL_DN0Is set to ‘1’ once the AHB bus matrix read buffer is disabled after getting a read buffer disable command from processor.
2DDRB_SW_WDSBL_DN0Is set to ‘1’ once the AHB bus matrix write buffer is disabled after getting a write buffer disable command from processor.
1DDRB_DS_RDSBL_DN0Is set to ‘1’ once the DS read buffer is disabled after getting a read buffer disable command from processor.
0DDRB_DS_WDSBL_DN0Is set to ‘1’ once the DS write buffer is disabled after getting a write buffer disable command from processor.