21.5.82 MSS DDR PLL Status Register

Table 21-90. MSSDDR_PLL_STATUS
Bit Number	Name	Reset Value	Description
[31:3]	Reserved	0	—
2	RCOSC_DIV2		Input from the System Controller, indicating whether the 50 MHz RC oscillator is running at 25 MHz or 50 MHz. 0: Running at 25MHz 1: Running at 50MHz
1	MPLL_LOCK	0	MPLL lock status. A LOCK signal is provided to indicate that the MPLL has locked on to the incoming signal. LOCK asserts High to indicate that the MPLL has achieved frequency and phase lock. Allowed values: 0: MPLL is not in lock 1: MPLL is in lock Microchip recommends that LOCK is only used for test and system status information, and is not used for critical system functions without thorough characterization in the host system. The precision of the LOCK discrimination can be adjusted using the LOCKWIN[2:0] controls. The integration of the LOCK period can be adjusted using the LOCKCNT[3:0] controls.
0	FAB_PLL_LOCK	0	If CLK_BASE is generated from a PLL in the fabric, this signal must be connected from the LOCK output of that PLL. When the FACC is going through its PLL initialization stage (either under system controller control or MSS master control), this signal is ANDed with the LOCK output of the MPLL. Only when both PLLs are in lock, is the system considered to be ready for switching to PLL-derived clock. If CLK_BASE is not derived from a fabric PLL, then the user must ensure that this signal is tied High at the fabric interface. Allowed values: 0: Fabric PLL is not in lock. 1: Fabric PLL is in lock or CLK_BASE is not derived from a fabric PLL.

[31:3]

Reserved

0

—

2

RCOSC_DIV2

Input from the System Controller, indicating whether the 50 MHz RC oscillator is running at 25 MHz or 50 MHz.

0: Running at 25MHz

1: Running at 50MHz

1

MPLL_LOCK

0

MPLL lock status.

A LOCK signal is provided to indicate that the MPLL has locked on to the incoming signal. LOCK asserts High to indicate that the MPLL has achieved frequency and phase lock. Allowed values:

0: MPLL is not in lock

1: MPLL is in lock

Microchip recommends that LOCK is only used for test and system status information, and is not used for critical system functions without thorough characterization in the host system. The precision of the LOCK discrimination can be adjusted using the LOCKWIN[2:0] controls. The integration of the LOCK period can be adjusted using the LOCKCNT[3:0] controls.

0

FAB_PLL_LOCK

0

If CLK_BASE is generated from a PLL in the fabric, this signal must be connected from the LOCK output of that PLL. When the FACC is going through its PLL initialization stage (either under system controller control or MSS master control), this signal is ANDed with the LOCK output of the MPLL. Only when both PLLs are in lock, is the system considered to be ready for switching to PLL-derived clock. If CLK_BASE is not derived from a fabric PLL, then the user must ensure that this signal is tied High at the fabric interface. Allowed values: 0: Fabric PLL is not in lock. 1: Fabric PLL is in lock or CLK_BASE is not derived from a fabric PLL.