21.5.37 MSS DDR PLL Status High Configuration Register
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:13] | Reserved | 0 | — |
| [12:8] | FACC_PLL_SSMF | 0 | Drives the spread spectrum modulation frequency (SSMF) input of the MPLL. The only allowable value to be programmed in this field is 0, as spread spectrum mode is not supported for the MPLL. |
| [7:6] | FACC_PLL_SSMD | 0 | Drives the spread spectrum modulation depth (SSMD) input of the MPLL. The only allowable value to be programmed in this field is 0, as spread spectrum mode is not supported for the MPLL. |
| 5 | FACC_PLL_SSE | 0 | Drives the SSE input of the MPLL. The only allowable value to be programmed in this field is 0, as spread spectrum mode is not supported for the MPLL. |
| 4 | FACC_PLL_PD | 0 | A PD signal is provided for lowest quiescent current. When PD is asserted, the MPLL powers down, and outputs are Low. PD has precedence over all other functions. |
| 2 | FACC_PLL_MODE_3V3 | 0x1 | Configures MPLL analog operational voltage. 1: 3.3 V 0: 2.5 V |
| 1 | FACC_PLL_MODE_1V2 | 0x1 | Configures the PLL core voltage. 1: 1.2 V Do not write to this field. |
| 0 | FACC_PLL_BYPASS | 0 | Powers down the MPLL core and bypasses it such that PLLOUT tracks REFCLK. |
Note: Do not change these register fields dynamically for 005 and 010 devices, see 21.5.1 System Registers Behavior for M2S005/010 Devices.