21.5.78 Device Status Register
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:7] | Reserved | 0 | |
| 6 | M3_DEBUG_ENABLE | 0x1 | Enables the debug access port (DAP) logic within the Cortex-M3 processor. The reset signal for this bit is SYSRESET_N. The read type is RO-U for this bit. This bit has the following meanings: 0: Debug block of Cortex-M3 is disabled and it is not possible to use a debugger to debug user firmware. 1: Debug block of Cortex-M3 is enabled and it is possible to use a debugger to debug user firmware. |
| 5 | M3_DISABLE | 0 | Disables/enables the Cortex-M3 processor. When this bit is 1, the Cortex-M3 processor is reset. When this is 0, the Cortex-M3 processor will be out of reset. |
| 4 | FLASH_VALID_SYNC | 0 | Asserted when FPGA fabric is valid. There is no reset signal for this bit. This bit has the following meanings: 0: FPGA fabric flash bits are valid and operational 1: FPGA fabric flash bits are not operational |
| 3 | WATCHDOG_FREEZE_SYNC | 0 | Freezes the watchdog counter. There is no reset signal for this bit. This bit has the following meanings: 0: Watchdog counter is not frozen 1: Watchdog counter is frozen (not counting down) |
| 2 | FF_IN_PROGRESS_SYNC | 0 | Indicates the FF_IN_PROGRESS STATE. There is no reset signal for this bit. |
| 1 | VIRGIN_PART | 0x1 | Indicates the device as virgin or non-virgin type. There is no reset signal for this bit. This bit has the following meanings: 0: Device is not a virgin part. It has been through a programming cycle to at least configure the factory settings 1: Device is a virgin part. It has never been through any programming cycle in and all internal flash bits are invalid |
| 0 | CORE_UP_SYNC | 0 | Indicates the status of the synchronized CORE_UP input from the system controller. There is no reset signal for this bit. |