21.5.105 IOMUXCELL_CONFIG[n] Configuration Register

Table 21-114. IOMUXCELL_CONFIG[n]
Bit NumberNameReset ValueDescription
[31:10]Reserved0
9MSS_IOMUXSEL5LOWER[N]0Used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL. Each bit of this bus is used together with the corresponding bit of MSS_IOMUXSEL5UPPER and MSS_IOMUXSEL5MID to form a 3-bit field. This field definition is in Table 21-115.
8MSS_IOMUXSEL5MID[N]0Used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL
7MSS_IOMUXSEL5UPPER[N]0Used to select the source of the OE port of the I/O cell corresponding to this IOMUXCELL
6:4MSS_IOMUXSEL4[N][2:0]0Used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL. This field definition is in Table 21-116.
3MSS_IOMUXSEL3[N]00: Output enable of interface MSS GPIO of IOMUXCELL goes to FPGA fabric core input

1: Output of interface serial comms of IOMUXCELL goes to FPGA fabric core input

2MSS_IOMUXSEL2[N]00: Output of interface MSS GPIO of IOMUXCELL goes to FPGA fabric core input

1: Output enable of interface serial comms of IOMUXCELL goes to FPGA fabric core input

1MSS_IOMUXSEL1[N]00: Input of interface MSS GPIO of IOMUXCELL comes from the output of interface FPGA fabric core

1: Input of interface MSS GPIO of IOMUXCELL comes from the I/O cell input

0MSS_IOMUXSEL0[N]00: Input of interface serial comms of IOMUXCELL comes from the output of interface FPGA fabric core

1: Input of interface serial comms of IOMUXCELL comes from the I/O cell input

Notes:

  • Bit 0, Bit 1, and Bit 2 in the following table refer to IOMUXSEL5LOWER, IOMUXCELL5MID, IOMUXCELL5UPPER respectively.
  • Do not change these register fields dynamically for 005 and 010 devices, see System Registers Behavior for M2S005/010 Devices.