21.5.36 MSS DDR PLL Status Low Configuration Register

This register is to be configured by flash bits only and you should not write to it while the source clock is active.

Table 21-42. MSSDDR_PLL_STATUS_LOW_CR
Bit Number	Name	Reset Value	Description
[31:30]	Reserved	0	—
[29:26]	FACC_PLL_LOCKCNT	0	Configures the MPLL LOCK counter value given by (2^ binary value + 5). For example, if the binary value is 0000, the LOCK counter value is 32, and if binary value is 1111, then its value is 1,048,576.
[25:23]	FACC_PLL_LOCKWIN	0	Configures the MPLL phase error window for LOCK assertion as a fraction of the divided reference period. Values are at typical PVT only and are not PVT compensated. 000: 500 ppm 100: 8000 ppm 001: 1000 ppm 101: 16000 ppm 010: 2000 ppm 110: 32000 ppm 011: 4000 ppm 111: 64000 ppm
[22:19]	FACC_PLL_RANGE	0	Configures the MPLL filter range. The bit definitions are in FACC_PLL_RANGE.
[18:16]	FACC_PLL_DIVQ	0x2	Configures the MPLL output divider value in order to generate the DDR clock. Output divider values are given by: 000: Divided by 1 001: Divided by 2 010: Divided by 4 011: Divided by 8 100: Divided by 16 101: Divided by 32 While it is possible to configure the MPLL output divider as ÷1, this setting must not be used when the DDR is operational. This is to ensure that the clock to the DDR has an even mark:space ratio.
[15:6]	FACC_PLL_DIVF	0x2	Configures the MPLL feedback divider value, which is given by the binary value +1. The binary value ranges from 0000000000, which is the divisor value of 1, to 1111111111, which is the divisor value of 1,024.
[5:0]	FACC_PLL_DIVR	0x1	Configures the MPLL reference divider value, which is given by binary value +1. For example, if the value is 000000, then the divisor value is 1 (000000 + 1). Both REFCLK and post-divide REFCLK must be within the range specified in the SmartFusion 2 datasheet.

Note: Do not change these register fields dynamically for 005 and 010 devices, see System Registers Behavior for M2S005/010 Devices.