21.5.85 DDRB Status Register
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:0] | DDRB_DEBUG_STATUS | 0x1 | Status of the internal ports of DDRBRIDGE. The bit definitions are as follows: Debug ports of the MSS DDR bridge: SYR_DDRB_DP[31:30] = DSG write buffer mode status SYR_DDRB_DP[29:28] = AHB bus write buffer mode status SYR_DDRB_DP[27:26] = HPDMA write buffer mode status SYR_DDRB_DP[25:23] = IDC read buffer mode status SYR_DDRB_DP[22:20] = DSG read buffer mode status SYR_DDRB_DP[19:17] = AHB bus read buffer mode status SYR_DDRB_DP[16:14] = HPDMA read buffer mode status SYR_DDRB_DP[13] = DSG write request to arbiter SYR_DDRB_DP[12] = AHB bus write request to arbiter SYR_DDRB_DP[11] = HPDMA write request to arbiter SYR_DDRB_DP[10] = IDC read req to arbiter SYR_DDRB_DP[9] = DSG read req to arbiter SYR_DDRB_DP[8] = AHB bus read req to arbiter SYR_DDRB_DP[7] = HPDMA read request to arbiter SYR_DDRB_DP[6] = AXI write address channel acknowledge to DSG write request SYR_DDRB_DP[5] = AXI write address channel acknowledge to AHB bus write request SYR_DDRB_DP[4] = AXI write address channel acknowledge to HPDMA write request SYR_DDRB_DP[3] = AXI write data channel acknowledge to DSG write request SYR_DDRB_DP[2] = AXI write data channel acknowledge to AHB bus write request SYR_DDRB_DP[1] = AXI write data channel acknowledge to HPDMA write request SYR_DDRB_DP[0] = Lock input to arbiter from AHB bus WCB |