21.5.103 Flush Configuration Register

Table 21-112. FLUSH_CR
Bit Number	Name	Description
[31:9]	Reserved
8	DDRB_INVALID_IDC	Allows the read buffer for the IDC master in the MSS DDR bridge to be invalidated. The read buffer is emptied once this pulse is detected. 0: No effect 1: Invalidate IDC read buffer
7	DDRB_INVALID_HPD	Allows the read buffer allocated for the AHB bus in the MSS DDR bridge to be invalidated. The read buffer is emptied once this pulse is detected. 0: No effect 1: Invalidate HPD read buffer
6	DDRB_INVALID_SW	Allows the read buffer for the high performance master in the MSS DDR bridge to be invalidated. The read buffer is emptied once this pulse is detected. 0: No effect 1: Invalidate AHB Bus read buffer
5	DDRB_INVALID_DS	Allows the read buffer for the DSG Master in the MSS DDR bridge to be invalidated. The read buffer is emptied once this pulse is detected. 0: No effect 1: Invalidate DSG read buffer
4	DDRB_FLSHSW	Allows the write buffer for the AHB bus in the MSS DDR bridge to be flushed. Data present in the write buffer is transferred to the MSS DDR bridgewrite arbiter interface when this pulse is detected. 0: No effect 1: Flush AHB bus write buffer
3	DDRB_FLSHHPD	Allows the write buffer for the HPD master in the MSS DDR bridge to be flushed. Data present in the write buffer is transferred to the MSS DDR bridge write arbiter interface when this pulse is detected. 0: No effect 1: Flush HPD write buffer
2	DDRB_FLSHDS	Allows the write buffer for the DSG master in the MSS DDR bridge to be flushed. Data in the write buffer is transferred to the MSS DDR bridge write arbiter when this pulse is detected. 0: No effect 1: Flush DSG write buffer
1	CC_FLUSH_CHLINE	Signal (pulse) to flush only one index in the cache memory. This signal is used to invalidate all tags of four sets at one index only. 0: No effect 1: Flush index
0	CC_FLUSH_CACHE	Signal (pulse) to flush cache memory. This signal is used to invalidate all tags of four sets at the same time. Allowed values: 0: No effect 1: Flush cache memory

[31:9]

Reserved

0

8

DDRB_INVALID_IDC

0

Allows the read buffer for the IDC master in the MSS DDR bridge to be invalidated. The read buffer is emptied once this pulse is detected.

0: No effect 1: Invalidate IDC read buffer

7

DDRB_INVALID_HPD

0

Allows the read buffer allocated for the AHB bus in the MSS DDR bridge to be invalidated. The read buffer is emptied once this pulse is detected.

0: No effect 1: Invalidate HPD read buffer

6

DDRB_INVALID_SW

0

Allows the read buffer for the high performance master in the MSS DDR bridge to be invalidated. The read buffer is emptied once this pulse is detected.

0: No effect 1: Invalidate AHB Bus read buffer

5

DDRB_INVALID_DS

0

Allows the read buffer for the DSG Master in the MSS DDR bridge to be invalidated. The read buffer is emptied once this pulse is detected.

0: No effect 1: Invalidate DSG read buffer

4

DDRB_FLSHSW

0

Allows the write buffer for the AHB bus in the MSS DDR bridge to be flushed. Data present in the write buffer is transferred to the MSS DDR bridgewrite arbiter interface when this pulse is detected.

0: No effect 1: Flush AHB bus write buffer

3

DDRB_FLSHHPD

0

Allows the write buffer for the HPD master in the MSS DDR bridge to be flushed. Data present in the write buffer is transferred to the MSS DDR bridge write arbiter interface when this pulse is detected.

0: No effect 1: Flush HPD write buffer

2

DDRB_FLSHDS

0

Allows the write buffer for the DSG master in the MSS DDR bridge to be flushed. Data in the write buffer is transferred to the MSS DDR bridge write arbiter when this pulse is detected.

0: No effect 1: Flush DSG write buffer

1

CC_FLUSH_CHLINE

0

Signal (pulse) to flush only one index in the cache memory. This signal is used to invalidate all tags of four sets at one index only. 0: No effect 1: Flush index

0

CC_FLUSH_CACHE

0

Signal (pulse) to flush cache memory. This signal is used to invalidate all tags of four sets at the same time. Allowed values: 0: No effect 1: Flush cache memory