21.5.9 Cache Region Control Register

Table 21-13. CC_REGION_CR
Bit Number Name Reset Value Description
[31:4] Reserved 0
3:0 CC_CACHE_REGION 0 Defines the cache region size. The bits have the following definitions:

Bit 0: First (lower) slot of 128 MB (0–128 MB)

Bit 1: Second slot of 128 MB (128–256 MB)

Bit 2: Third slot of 128 MB (25–384 MB)

Bit 3: Fourth (upper) slot of 128 MB (384–512 MB)

For 128 MB configuration, only one bit out of four will be set to select one of the blocks as cacheable.

For 256 MB configuration, bits [1:0] are set to select the lower 256 MB as cacheable, bits [3:2] are set to select the lower 256 MB as cacheable.

For 512 MB configuration all four bits are set to select entire 512 MB as cacheable.