21.5.8 Cache Configuration Register
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:3] | Reserved | 0 | |
| 2 | CC_CACHE_LOCK | 0 | Allows the cache lock to be enabled. The allowed values: 0: Disabled 1: Enabled |
| 1 | CC_SBUS_WR_MODE | 0 | Allows debug mode SBUS writes to cache memory to be enabled. The allowed values: 0: Disabled 1: Enabled |
| 0 | CC_CACHE_ENB | 0 | Allows the cache to be disabled. The allowed values: 0: Disabled 1: Enabled |