21.5.77 ETM Count High Register
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:28] | Reserved | 0 | |
| [27:25] | ETMINTSTAT | 0 | Indicates the interrupt status. The following bit definitions mark the interrupt status of the current cycle: 000: No status 001: Interrupt entry 010: Interrupt exit 011: Interrupt return 100: Vector fetch and stack push ETMINTSTAT entry or return is asserted in the first cycle of the new interrupt context. Exit occurs without ETMIVALID. |
| [24:16] | ETMINTNUM | 0 | Marks the interrupt number of current execution context. |
| [15:0] | ETMCOUNT_47_32 | 0 | Indicates the 47 to 32 of timestamp value (TSVALUEB) from the Cortex-M3 processor. |