[31:7] |
Reserved |
0 |
— |
6 |
DDRB_IDC_RBEMPTY |
0 |
When set to "1", indicates that the read
buffer of the IDC master does not have valid data. |
5 |
DDRB_HPD_RBEMPTY |
0 |
When set to "1", indicates that the read
buffer of the HPDMA master does not have valid data. |
4 |
DDRB_HPD_WBEMPTY |
0 |
When set to "1", indicates that the write
buffer of the HPDMA master does not have valid data. |
3 |
DDRB_SW_RBEMPTY |
0 |
When set to "1", indicates that the read
buffer of the AHB bus matrix master does not have valid data. |
2 |
DDRB_SW_WBEMPTY |
0 |
When set to "1", indicates that the write
buffer of the AHB bus matrix master does not have valid data. |
1 |
DDRB_DS_RBEMPTY |
0 |
When set to "1", indicates that the read
buffer of the DSG master does not have valid data. |
0 |
DDRB_DS_WBEMPTY |
0 |
When set to "1", indicates that the write
buffer of the DSG master does not have valid data. |