21.5.57 MSS DDR Bridge Buffer Empty Status Register

Table 21-65. DDRB_BUF_EMPTY_SR
Bit NumberNameReset ValueDescription
[31:7]Reserved0—
6DDRB_IDC_RBEMPTY0When set to "1", indicates that the read buffer of the IDC master does not have valid data.
5DDRB_HPD_RBEMPTY0When set to "1", indicates that the read buffer of the HPDMA master does not have valid data.
4DDRB_HPD_WBEMPTY0When set to "1", indicates that the write buffer of the HPDMA master does not have valid data.
3DDRB_SW_RBEMPTY0When set to "1", indicates that the read buffer of the AHB bus matrix master does not have valid data.
2DDRB_SW_WBEMPTY0When set to "1", indicates that the write buffer of the AHB bus matrix master does not have valid data.
1DDRB_DS_RBEMPTY0When set to "1", indicates that the read buffer of the DSG master does not have valid data.
0DDRB_DS_WBEMPTY0When set to "1", indicates that the write buffer of the DSG master does not have valid data.