21.5.53 DCode Transaction Count Control Status Register

Table 21-61. CC_DC_TRANS_CNTR_SR
Bit Number	Name	Reset Value	Description
[31:0]	CC_DC_TRANS_CNT	0	Keeps count of the total number of transaction counts processed by the cache engine (cacheable and non-cacheable reads on DCode bus). This counter is put to the reset value by setting CC_DC_TRANS_CNTCLR bit.

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