21.5.20 M3 Configuration Register
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:29] | Reserved | 0 | |
| 28 | M3_MPU_DISABLE | 0 | When set, disables the memory protection unit (MPU) within the Cortex-M3 processor. |
| [27:26] | STCLK_DIVISOR | 0x3 | Configures the amount of division to be performed on M3_CLK, in order to generate the STCLK input for the Cortex-M3 processor. This is used to control the frequency of STCLK. 00: M3_CLK/4 01: M3_CLK/8 10: M3_CLK/16 11: M3_CLK/32 |
| [25:0] | STCALIB[25:0] | 0x2000000 | Used as the STCALIB input for the Cortex-M3 processor. It determines the rollover value for the internal SysTick timer of the Cortex-M3 processor. The bit definitions for this field are as follows: STCALIB[25] – NOREF bit of SysTick Calibration Value Register; 1 indicates STCLK is not provided. STCALIB[24] – SKEW bit of SysTick Calibration Value Register; 1 indicates calibration value is not exactly 10 ms. STCALIB[23:0] – TENMS field of SysTick Calibration Value Register; reload value to use for 10 ms timing. |
Note: Do not change these register fields dynamically for 005 and 010 devices, see 21.5.1 System Registers Behavior for M2S005/010 Devices.