21.5.55 MSS DDR Bridge High Performance DMA Master Error Address Status Register
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:0] | DDRB_HPD_ERR_ADD | 0 | If a write transfer initiated at the MSS DDR bridge arbiter interface to empty data present in the write buffer of the HPDMA master which receives an error response, the address for which the error response is received is placed in this register. Address indicates TAG value for which error response is received. The following values are updated in this register as per buffer size: 16 bytes: DDRB_HPD_ERR_ADR[31:4] = TAG, DDRB_HPD_ERR_ADR[3:0] = 0000 32 bytes: DDRB_HPD_ERR_ADR[31:5] = TAG[27:1], DDRB_HPD_ERR_ADR[4:0] = 0000. |