21.5.50 DCode Miss Control Status Register

Table 21-58. CC_DC_MISS_CNTR_SR
Bit Number	Name	Reset Value	Description
[31:0]	CC_DC_MISS_CNT	0	Counts the total number of cache misses that occurs on the cacheable region through the DCode bus. Rolls back after maximum value. This counter is put to the reset value by setting CC_DC_MISS_CNTCLR.

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