21.5.35 MAC Configuration Register
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:9] | Reserved | 0 | |
| [8:5] | RGMII_TXC_DELAY_SEL | 0 | Specifies how many delay taps the RGMII transmit clock passes through 0 to 15 |
| [3:2] | ETH_PHY_MODE | 0 | Indicates the Ethernet PHY mode. Allowed values: 000: RMII 001: Reserved 010: TBI 011: MII 100: GMII Other values: Reserved |
| [1:0] | ETH_LINE_SPEED | 0 | Indicates the Ethernet line speed. Allowed values: 00: 10 Mbps 01: 100 Mbps 10: 1,000 Mbps 11: Reserved |