21.5.32 eSRAM PIPELINE Configuration Register

Table 21-38. ESRAM_PIPELINE_CR
Bit Number	Name	Reset Value	Description
[31:1]	Reserved	0
0	ESRAM_PIPELINE_ENABLE	0x1	Controls the pipeline in the read path of eSRAM memory. Allowed values: 0: Pipeline is bypassed 1: Pipeline is present in the memory read path

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