21.5.11 MSS DDR Bridge Buffer Timer Control Register
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:10] | Reserved | 0 | — |
| [9:0] | DDRB_TIMER | 0x3FF | 10-bit timer interface used to configure the timeout register in the write buffer module. Once timer reaches the timeout value, a flush request is generated by the flush controller and if response has been received for previous write request from write arbiter, this request is posted to the write arbiter. This register is common for all buffers. The value in this register is in terms of number of M3_CLK clocks. |