21.5.41 MSS DDR Clock Calibration Control Register

Table 21-49. MSSDDR_CLK_CALIB_CR
Bit Number	Name	Reset Value	Description
[31:1]	Reserved	0
0	FAB_CALIB_START	0	Writing to this bit causes a one clock tick pulse to be generated on FABCALIBSTART. This is used to start an FPGA fabric calibration test circuit.

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