21.5.39 MSS DDR Fabric Alignment Clock Controller Configuration Register 2
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:14] | Reserved | 0 | — |
| 13 | MSS_XTAL_RTC_EN | 0x1 | Enable signal for auxiliary crystal oscillator (RTC crystal oscillator) |
| 12 | MSS_XTAL_EN | 0x1 | Enables the signal for the main crystal oscillator. If the main crystal oscillator is selected as the MSS Flash*Freeze clock source, this bit must be asserted at all times (even when not in Flash*Freeze mode). 1: Enable 0: Disable |
| 11 | MSS_CLK_ENVM_EN | 0x1 | Enables internal eNVM RC oscillator. Configure this field statically. Do not write to this field while the source clock is active. |
| 10 | MSS_1MHZ_EN | 0x1 | Enables the signal for the 1 MHz RC oscillator. If the 1 MHz RC oscillator is selected as the MSS Flash*Freeze clock source, this bit must be asserted at all times (even when not in Flash*Freeze mode). 1: Enable 0: Disable |
| 9 | MSS_25_50MHZ_EN | 0x1 | Enables the signal for the 50 MHz RC oscillator. If the 50 MHz RC oscillator is selected as the MSS Flash*Freeze clock source, this bit must be asserted at all times (even when not in Flash*Freeze mode). 1: Enable 0: Disable |
| [8:6] | FACC_STANDBY_SEL | 0 | Contains the select lines for the three 2 to
1 no-glitch multiplexers, which implement the 4 to 1 no-glitch standby MUX
function. This is used to allow one of four possible clocks to proceed through
to the MSS during FACC PLL Initialization Time. There are two MUXes in the
first rank, and these feed into a third MUX in the second rank. Bit 6 feeds into one of the first rank 2 to 1 MUXes (Standby MUX 0) and is defined as follows: 0: MUX 0 output comes from RCOSC_25_50MHZ 1: MUX 0 output comes from XTLOSC_CLK Bit 7 feeds into one of the first rank 2 to 1 MUXes (Standby MUX 1). Bit 7 must always be 0 and defined as follows: 0: MUX 1 output comes from RCOSC_1MHZ Bit 8 feeds into the second rank 2 to 1 MUX (Standby MUX 2) and is defined as follows: 0: MUX 2 output comes from MUX 0 1: MUX 2 output comes from MUX 1 Do not write to this field while the standby clock is active. |
| 5 | FACC_PRE_SRC_SEL | 0 | Must always be 0, and defined as follows: 0: RCOSC_1MHZ is fed through to the source no-glitch clock multiplexer. |
| [4:2] | FACC_SRC_SEL | 0 | Contains the select lines for the three 2 to
1 no-glitch multiplexers, which implement a 4 to 1 no-glitch source MUX
function. There are two MUXes in the first rank, and these feed into a third
MUX in the second rank. Bit 2 feeds into one of the first rank 2 to 1 MUXes (Source MUX 0) and is defined as follows: 0: MUX 0 output comes from RCOSC_25_50MHZ 1: MUX 0 output comes from XTLOSC_CLK Bit 3 feeds into one of the first rank 2 to 1 MUXes (Source MUX 1) and is defined as follows: 0: MUX 1 output comes from RCOSC_1MHZ 1: MUX 1 output comes from MPLL_OUT_CLK Bit 4 feeds into the second rank 2 to 1 MUX (Source MUX 2) and is defined as follows: 0: MUX 2 output comes from MUX 0 1: MUX 2 output comes from MUX 1 When switching any of the no-glitch MUXes, both the clock being switched from and the clock being switched to must be running. Do not write to this field while the source clock is active. |
| [1:0] | RTC_CLK_SEL | 0 | Indicates which of the possible clocks are to
be configured as the source of the MSS RTC clock. The allowed values are as
follows: 00: RTC_CLK comes from XTLOSC_CLK 01: RTC_CLK comes from RCOSC_1MHZ 10: RTC_CLK comes from RCOSC_25_50MHZ 11: RTC_CLK comes from RTC_XTLOSC_CLK The reset signal for this bit is SYSRESET_N. |