21.5.33 MSS Interrupt Enable Control Register

Table 21-39. MSS_IRQ_ENABLE_CR
Bit Number	Name	Reset Value	Description
[31:20]	Reserved	0
[19:10]	DDRB_INTERRUPT_EN	0x3FF	Used to mask the MSS DDR bridge interrupt to the Cortex-M3 processor
[9:7]	CC_INTERRUPT_EN	0x7	Used to mask the cache interrupt to the Cortex-M3 processor
[6:0]	SW_INTERRUPT_EN	0x7F	Used to mask the AHB bus interrupt to the Cortex-M3 processor

Note: Do not change these register fields dynamically for 005 and 010 devices, see 21.5.1 System Registers Behavior for M2S005/010 Devices.

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