| [31:16] | Reserved | 0 | |
| 15 | NVM1_UPPER_WRITE_ALLOWED | 0x1 | When set, indicates that the masters who have read access can have write access to the upper protection region of eNVM1. This is updated by the user flash row bit. |
| 14 | NVM1_UPPER_OTHERS_ACCESS | 0x1 | When set, indicates that the other masters can access the upper protection region of eNVM1.This is set by the user flash row bit. |
| 13 | NVM1_UPPER_FABRIC_ACCESS | 0x1 | When set, indicates that the fabric can access the upper protection region of eNVM1. This is set by the user flash row bit. |
| 12 | NVM1_UPPER_M3ACCESS | 0x1 | When set, indicates that the Cortex-M3 processor can access the upper protection region of eNVM1. This is updated by the user flash row bit. |
| 11 | NVM1_LOWER_WRITE_ALLOWED | 0x1 | When set, indicates that the masters who have read access can have write access to the lower protection region of eNVM1. This is set by the user flash row bit. |
| 10 | NVM1_LOWER_OTHERS_ACCESS | 0x1 | When set, indicates that the other masters can access the lower protection region of eNVM1. This is set by the user flash row bit. |
| 9 | NVM1_LOWER_FABRIC_ACCESS | 0x1 | When set, indicates that the fabric can access the lower protection region of eNVM1.This will be set by user flash row bit. |
| 8 | NVM1_LOWER_M3ACCESS | 0x1 | When set, indicates that the M3 can access the lower protection region of eNVM1. This will be set by the user flash row bit. |
| 7 | NVM0_UPPER_WRITE_ALLOWED | 0x1 | When set, indicates that the masters who have read access can have write access to the upper protection region of eNVM0. This will be set by the user flash row bit. |
| 6 | NVM0_UPPER_OTHERS_ACCESS | 0x1 | When set, indicates that the other masters can access the upper protection region of eNVM0. |
| 5 | NVM0_UPPER_FABRIC_ACCESS | 0x1 | When set, indicates that the fabric can access the upper protection region of eNVM0. This will be set by the user flash row bit. |
| 4 | NVM0_UPPER_M3ACCESS | 0x1 | When set, indicates that the M3 can access the upper protection region of eNVM0. This will be set by the user flash row bit. |
| 3 | NVM0_LOWER_WRITE_ALLOWED | 0x1 | When set, indicates that the masters who have read access can have write access to the lower protection region of eNVM0. This will be set by the user flash row bit. |
| 2 | NVM0_LOWER_OTHERS_ACCESS | 0x1 | When set, indicates that the other masters can access the lower protection region of eNVM0. This will be set by the user flash row bit. |
| 1 | NVM0_LOWER_FABRIC_ACCESS | 0x1 | When set, indicates that the fabric can access the lower protection region of eNVM0. This will be set by the user flash row bit. |
| 0 | NVM0_LOWER_M3ACCESS | 0x1 | When set, indicates that the M3 can access the lower protection region of eNVM0. This will be set by the user flash row bit. |
