21.5.27 Peripheral Clock MUX Select Control Register
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:3] | Reserved | 0 | |
| 2 | TRACECLK_DIV2_SEL | 0 | Selects whether the Cortex-M3 processor trace clock source is M3_CLK or M3_CLK/2. Allowed values: 0: M3_CLK selected as source of TRACECLKIN_I 1: M3_CLK/2 selected as source of TRACECLKIN_I |
| 1 | SPI1_SCK_FAB_SEL | 0 | Selects the SPI1_SCK from the fabric or I/O pads. Allowed values: 0: SPI1_SCK clock from I/O pads is selected and fed to SPI1 1: SPI1_SCK clock from the fabric is selected and fed to SPI1 |
| 0 | SPI0_SCK_FAB_SEL | 0 | Selects the SPI0_SCK from the fabric or I/O pads. Allowed values: 0: SPI0_SCK clock from I/O pads is selected and fed to SPI0 1: SPI0_SCK clock from fabric is selected and fed to SPI0 |
Note: Do not change these register fields dynamically for 005 and 010 devices, see 21.5.1 System Registers Behavior for M2S005/010 Devices.