21.5.14 MSS DDR Bridge Configuration Register
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:24] | Reserved | 0 | |
| [23:20] | DDR_IDC_MAP | 0 | Sets the DSG interface to DDR address space mapping mode 0–15. |
| [19:16] | DDR_SW_MAP | 0 | Sets the AHB bus master to DDR address space mapping mode 0–15. |
| [15:12] | DDR_HPD_MAP | 0 | Sets the HPDA master to DDR address space mapping mode 0–15. |
| [11:8] | DDR_DS_MAP | 0 | Sets the DSG master to DDR address space mapping mode 0–15. |
| 7 | DDRB_BUF_SZ | 0x1 | Configures the write buffer and read buffer size as per DDR burst size. This port is common for all buffers. IDC read buffer has fixed size of 32 bytes. Other buffers can be configured to 16-byte or 32-byte size. 0: Buffer size is configured to 16 bytes 1: Buffer size is configured to 32 bytes |
| 6 | DDRB_IDC_EN | 0x1 | Allows the read buffer for IDC interface in MSS DDR bridge to be disabled. Allowed values: 0: Disabled 1: Enabled |
| 5 | DDRB_SW_REN | 0x1 | Allows the read buffer for AHB BUS master in MSS DDR bridge to be disabled. Allowed values: 0: Disabled 1: Enabled |
| 4 | DDRB_SW_WEN | 0x1 | Allows the write combining buffer for AHB bus master in MSS DDR bridge to be disabled. Allowed values: 0: Disabled 1: Enabled |
| 3 | DDRB_HPD_REN | 0x1 | Allows the read buffer for high performance DMA master in MSS DDR bridge to be disabled. Allowed values: 0: Disabled 1: Enabled |
| 2 | DDRB_HPD_WEN | 0x1 | Allows the write combining buffer for high performance DMA master in MSS DDR bridge to be disabled. Allowed values: 0: Disabled 1: Enabled |
| 1 | DDRB_DS_REN | 0x1 | Allows the read buffer for DSG master in MSS DDR bridge to be disabled. Allowed values: 0: Disabled 1: Enabled |
| 0 | DDRB_DS_WEN | 0x1 | Allows write combining buffer for DSG master in MSS DDR bridge to be disabled. Allowed values: 0: Disabled 1: Enabled |