14.8.221 DLEC

This component is supported by ACT 1, ACT 2, ACT 3, 3200DX, MX, Accelerator families.

Figure 14-253. DLEC Logic Diagram
  • Function: Data Latch with active low Enable and Clock
  • Input: D, E, G
  • Output: Q
Table 14-418. Truth Table
EGQn+1
1XQ
X1Q
00D
Table 14-419. Modules
FamilySeqComb
ACT 1/MX1
Others1