14.8.227 DLM3A

This component is supported by ACT 2, ACT 3, 3200DX, MX, Accelerator families.

Figure 14-259. DLM3A Logic Diagram
  • Function: Data Latch with 4-input Multiplexed Data, and active low Clock
  • Input: D0, D1, D2, D3, S0, S1, G
  • Output: Q
Table 14-430. Truth Table
S1S0GQn+1
XX1Q
000D0
010D1
100D2
110D3
Table 14-431. Modules
FamilySeqComb
All listed1