14.8.224 DLM2A

This component is supported by ACT 1, MX families.

Figure 14-256. DLM2A Logic Diagram
  • Function: Data Latch with 2-input Multiplexed Data and Clear, and Active-Low Clock
  • Input: A, B, CLR, S, G
  • Output: Q
Table 14-424. Truth Table
CLRSGQn+1
1XX0
0X1Q
000A
010B
Table 14-425. Modules
FamilySeqComb
ACT 1/MX1