14.8.182 DFME3B

This component is supported by Accelerator family.

Figure 14-214. DFME3B Logic Diagram
  • Function: D-Type Flip-Flop with 2-input Multiplexed Data, falling-edge triggered Clock, and active-low Enable and Clear
  • Input: CLK, A, B, S, E, CLR
  • Output: Q
Table 14-340. Truth Table
CLRESCLKQn+1
0XXX0
11XXQ
100A
101B
Table 14-341. Modules
FamilySeqComb
All listed1