14.8.220 DLEB

This component is supported by ACT 1, ACT 2, ACT 3, 3200DX, MX, Accelerator families.

Figure 14-252. DLEB Logic Diagram
  • Function: Data Latch with active high Enable, and active low Clock
  • Input: D, E, G
  • Output: Q
Table 14-416. Truth Table
EGQn+1
0XQ
X1Q
10D
Table 14-417. Modules
FamilySeqComb
ACT 1/MX—1
Others1—